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High-Speed Serial Bus (GMSL/FPD-Link) Layout for ADAS Controller PCBA

The data architecture of the vehicle is changing considerably with the evolution of Advanced Driver Assistance Systems ADAS (Level 3+ conduite autonome). The systems in modern-day ADAS controllers (that are typically outfitted with 8MP cameras, LiDARs, RADARs) have to process a huge flow of uncompressed high-resolution visual data in absolute real-time.
 
The automotive industry relies on high-speed serializer/deserializer (SerDes) technologies, such as GMSL (Gigabit Multimedia Serial Link) et FPD-Link (Flat Panel Display Link), to deliver multi-gigabit data streams through the vehicle chassis to the CPU. Those technologies are used in rear-view camera systems and also in other sensors.
 
A carte de circuit imprimé assembly (PCBA) cannot simply look like a series of point-to-point connections. Certain data rates ranging from 6 Gbps to 12 Gbps/channel are involved. Instead, each trace operates less like a wire and more like a high-frequency transmission line, with any geometric or material imperfection having the potential to severely degrade signal quality, generate automotive electromagnetic compatibility (EMC) violations, or cause system failure.
 
To design a robust controller for an ADAS, the hardware layout strategy must strongly comply with impedance control, via architecture, EMI suppression, high-speed automotive components, and functional safety power design.
High-Speed Serial Bus (GMSLFPD-Link) Layout for ADAS PCBA

High-Speed Bus Architecture in ADAS Explained

FPD-Link signalling and GMSL must be considered by all for layout constraints. The camera transmits video to the l'alimentation électrique via a differential pair or coaxial cable (power-over-coax architecture). Powering DC and a bidirectional control channel (SPI/I2C) at lower speeds share the same medium.
 
Antenna system performance depends on the impedances at which terminals are connected to the radiating element of the antenna, otherwise referred to as the strained impedance matching. When the antenna does not see a matched impedance within allowable limits, there will be the formation of a boundary layer at the antenna due to the reflection of the energy back, which causes intersymbol interference (ISI). Due to ISI, the BER rises too high to be acceptable.

The Foundation: Transmission Line Impedance and Material Selection

Before routing a single trace, you must define the physical medium. For differential pairs, the target is 100 ohms; for single-ended coax, 50 ohms. This impedance must be maintained from the SerDes IC pin to the auto-grade connector.
 

Why Low-Loss Materials Matter

Régulière FR-4 glass-epoxy laminates are quite unsuitable for GMSL and FPD-Link routing for distances greater than a few cm. The FR-4 dielectric’s Df value has a high factor of approximately 0.02, while the Dk changes with frequency. This characteristic causes high-frequency signals to decay rapidly and assists in smoothing edge transitions during digital switching.
 
High-speed automotive applications maintain signal integrity with the help of mid-loss to low-loss thermoset resin laminate material such as Panasonic Megtron 6, Isola I-Speed or comparable Rogers materials. The Dk of the advanced substrates remains quite constant over a temperature range of about -40 to +125ºC. These items are manufactured to have a dissipation factor (Df) of less than 0.004.
 
Standard coarse glass textiles can cause variations of Dk either periodically or spatially. This can occur when signal traces cross over from regions of high glass density into resin-rich voids. Changes in dielectric properties create unexpected variations in the propagation delay. Due to this, the differential signal pair’s phase is skewed, and this can reduce the performance and quality of auto-communication.

Critical Differential Pair Routing: Intra-Pair and Inter-Pair Matching

High-speed buses like GMSL and FPD-Link rely on differential signaling (P and N lines) to reject common-mode noise. The golden rule for routing these is maintaining Phase Alignment.
 

Controlling Intra-Pair Skew (< 5ps)

For instances of GMSL/FPD-Link high-end generations, the intra-pair skew should be < 5ps. It is defined as the time of arrival difference of the P line and N line of the same differential pair. When picks are made across a board, and the trace changes direction, the inner trace has a shorter path than the outer trace. In order to rectify the source of mismatch, a compensation tuning phase should be introduced as close as possible to the source of mismatch.
 
To prevent reducing the impedance of localized areas, apply a structure that resembles the tapered design of a transmission line in series with your impedances.
ADAS controller PCBA on Phase compensation bump
The compensation structure should not have big gaps, as it may lead to a mismatch if it is located beyond the bend (nearby). Not controlling a skew in the differential signal that passes through a long-trace run will cause it to degrade to an Off-Balance signal (or Common-mode signal). A strong radiation field could occur from such a signal that will interfere with your EMC tests.
 

Inter-Pair Matching for Camera Arrays

To maintain quality, the single channel remains protected by intra-pair matching, whilst inter-pair matching regulates the length delta of distinctive camera channels entering the same deserializer host. Multi-camera surround view systems need strong hardware synchronization of localized video frames. Layout designers must ensure that trace length variations between neighbouring GMSL channels are well controlled within a tight tolerance band provided by the chip maker in order to avoid failure on the ADAS processor because of frame-buffer synchronization problems. In general, in practice, this is within 10mm to 15mm of electrical length.

Layer Transitions: Mastering Via Stub Control and Back-Drilling

In a 10+ layer ADAS controller that is tightly packed, transitions between board layers are essential. Yet, each via leads to an inductive and capacitive discontinuity that jeopardizes high-speed signals.
 

The Danger of Via Stubs

When a high-speed signal travels to an inner layer from the top layer via a copper-plated trou de passage, the part of the via that extends beyond the destination layer down to the bottom of the board is a residual stub. Stubs act as a resonant transmission line in an open circuit.
The serving signal can treat the stub as a court-circuit at some quarter-wavelength frequency. This entraps energy and creates a significant notch filter in the channel’s insertion loss.
resonant frequency
As indicated above, this is the resonant frequency.
Stub length – where (L) and the material relative permittivity (εr). Signals will suffer enormously from speed and distortion if there is a via stub of only 30 mil (0.76 mm).
 

The Solution: Controlled Back-Drilling

Due to the high-density nature of ADAS controllers that utilize 10, 12, or more layers, back-drilling is commercially the most viable and electronically the most effective weapon against via stubs. The laminated multi-layer board goes through a plating operation through all layers, and after that, a drilled hole takes place with a bigger drill. The back part of the bit bores into the via, effectively cutting off the copper stub.
 
In a high-end FS Tech stackup, the distance from the inner destination layer to the end of the drilled cavity, also known as stub length, is stringently restricted to a minimum of 2 mils and a maximum of 5 mils. It effectively eliminates any quarter-wave resonance issues all the way to 20 GHz for an ultra-clean SerDes interface.
Structural cross-section of differential signal vias in multilayer high-speed PCB

Automotive EMC Compliance: EMI Suppression and Shielding

Standards for electromagnetic compatibility, particularly CISPR 25 Class 5 emissions, will require automotive electronics to be exceptionally stringent. In PCB layout design of circuits with gigabit serial interfaces, proper care must be taken to avoid electrical interference with other sensitive circuits.
 

Strategically Placing Common-Mode Filters (CMF)

Even with good practice in differential pair design and impedance matching, a small amount of common-mode noise can still occur due to slight misbalances in the driver, the composants, and slight asymmetries in routing. According to industry best practices, the common-mode filter (CMF), which should be automotive-grade and high-frequency, should ideally be located as close to the connector interface as possible to prevent unwanted noise propagation through the vehicle’s long cable harnesses.
 
The selected common-mode filter (CMF) must have a cutoff frequency that is significantly larger than the operating frequency of the differential data channel to avoid degrading the signal integrity while providing good common-mode attenuation for cellular, GNSS and telematics, etc. Automotive-grade CMFs generally provide attenuation above twenty decibels.
 
During PCB layout design, the area located underneath the coussinets of the CMF components needs attention. Removing the reference plane or local cancellation beneath the pads could help minimize additional parasitic capacitance from large SMT pads. Due to this, the filter region maintains a constant transmission-line impedance that eliminates signal discontinuities, which would otherwise produce response degradation and reflections.
 

Shielding the Connector Interface

The main EMC boundary on an ADAS Assemblage de PCB is the automotive connector interface or Rosenberger HSD FAKRA or HMT. The connector pin interface provides an interface that is not planar and causes an effective discontinuity that causes an impedance mismatch. This makes the transmission line susceptible to external noise while itself radiating unwanted signals.
 
To ensure signal integrity and compliance with automotive emissions regulations, the following shielding limits must be implemented.
high-speed serial bus shielding layout
The location and orientation of the connector play a significant role in controlling high-frequency return currents. The connector breakout area’s surface-mounted pads may create capacitance that alters differential impedance characteristics discrimination and degrades high-speed SerDes signal performance. The designer has indicated the reference plane below the signal pads should be modified to create controlled impedance compensation areas. Extra shielding envelopes the connector interface to contain the electromagnetic energy, thus preventing coupling into low-speed circuits and car wiring harness.

ISO 26262 Functional Safety: Redundant Power and Monitoring

An automotive safety integrity level ADAS controller is an ASIL-rated system. If a camera bus has an instance of hardware failure or a corrupted data stream, that can cause an incorrect steer or brake command. Hence, the SerDes system’s power infrastructure must be robust, monitored, and isolated.
 

Power delivery redundancy and coax isolation

The camera module receives an injection of direct current voltage onto the high-speed signalling lines in Power-over-Coax (PoC) or Power-over-Differential systems. The sensor will instantly go blind if this power rail collapses or short-circuits.
 
Establishing redundant power paths is necessary for compliance with ISO 26262 functional safety requirements. The main PMIC divides the PDN into independent current-limited channels for each external sensor. The injection network employs a complex arrangement of wideband inductors and ferrites to provide a high impedance in order to avoid interference with the gigabit data stream, while also providing a current pass of several hundred mA DC. To prevent one side of the differential pair from being biased over the other, these components must be laid out symmetrically.
ADAS controller ASIL-RATED Functional Safety ISO26262

Continuous Voltage and Diagnostic Monitoring

Relying on a low-voltage power rail, the internal SerDes cores require monitoring for ISO 26262 diagnostic coverage compliance. Supply rails like 0.8V, 1.2V and 1.8V have very narrow noise margins. As a result, a slight dip in voltage can disturb PLL operation. Thus, there can be failures like video stream dropouts. Automotive-grade window voltage supervisors offer continuous monitoring of a critical power rail signal and generate a non-maskable interrupt (NMI) or system reset when the voltage moves out of the specified tolerance (±2% to ±5%).
 
The camera module power-over-coax lines are protected with high-side current monitors and inline shunt resistors. The current is constantly monitored by these. In case of short-circuiting or failure of the cable or connector, they quickly disconnect the channel so that other sensors do not get disturbed. Digital sensors are monitoring temperature in the deserializer ICs for maintaining the thermal profile. With the rise in temperature, $$D$$ de Matériau du circuit imprimé changes and copper trace resistance increases. When a safety controller has access to the real-time temperature level, it can perform signal equalization (or downgrade safety controller performance) ahead of compromise in signal integrity.

10-layer Automotive Stackup Architecture

The underlying layer stackup needs to be balanced to integrate all these strict layout rules so neatly. An asymmetrical layer stack with layers unsymmetrical can cause the PCB to warp after high-temperature soudure par refusion processes in automotive assemblies.
 
Here is an engineering drawing of a high-performance automotive stackup which has 10 layers specifications for high-speed ADAS SerDes.
Layer NumberType of LayersMain Functionality And Routing Rules
Layer 1 (Top)Indication / PartsHigh-speed connectors, passive components, IC breakouts.
Layer 2PlaneReference plane of solid digital ground (gnd). Not at all split.
Layer 3SignalHigh-speed GMSL / FPD-Link. Differential Routing Channel 1
Layer 4PlaneSolid digital ground (GND) or clean power plane.
Layer 5PuissancePower rails that are segmented heavily.
Layer 6Power / SignalSignals for control based on low-speed and diagnosis traces
Layer 7PlaneSolid Digital Ground (GND) reference plane.
Layer 8SignalChannel 2 of a GMSL / FPD-Link to route differential signalling
Layer 9PlaneReference plane of solid digital ground.
Layer 10 (Bottom)Signal / StaticNetworks and additional components of PoC filters.
 

Best Practices for Stack Design

  • Orthogonal Routing: Signal layers (e.g., Layers 3 and 8) must be routed orthogonally (perpendicularly) to adjacent layers to eliminate vertical broadside crosstalk.
  • Core/Core Symmetry: Match the thickness of the prepregs and cores on the top and bottom halves of the board to prevent warping.
  • Ground Planning: Dedicate layers to solid planes for shielding and low-inductance return paths.

Conclusion

According to the article, appropriate application-level routing and PCB material selection successfully maintained the design signal integrity. This application will be stable and functionally safe using these technologies. A design for EMI suppression shielding and power monitoring has been made ISO 26262 compliant. As a result, the Engineering and PCB Design teams take this requirement into account during design, resulting in successful first-pass manufacturing. It helps engineers achieve a high standard, such as CISPR 25 Class 5, and also reliable ADAS hardware for driverless cars.
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FAQs about Automotive ADAS Controller PCBA

  • The dielectric constant of standard FR-4 (a component likely constructed out of copper clad) has been confirmed to be quite stable. When transmitting data, losses cause attenuation of the signal itself, rounding of digital switching edges and unpredictable phase skew. FR-4 highly degrades signals at high data rates (6 Gbps to 12 Gbps+). To ensure clear eye diagrams over long distances, the $$D$$ of low-loss materials used in the high-speed ADAS controller must be less than 0.004.
  • The positive and negative lines of a differential pair can develop a mismatch in physical length, which is known as intra-pair skew. Trace corners and component breakouts frequently produce this effect. In order to compensate, designers add delay-matching structures (“bumps”) to the shorter trace. The bumps need to be positioned as closely as possible to the exact location of the mismatch. Furthermore, the bumps must have a loose high-radius geometry to avoid localized drops in impedance.
  • As a high-speed signal transitions from a top layer to an inner layer through a via, the residual un-routed part of the via down to the bottom layer forms a “stub.” This stub acts like a resonant transmission line that can trap signal energy at some frequency, which forms a very severe notch filter in the Insertion loss profile. The excess copper stub is removed through Back-drilling by using a larger drill bit, which eliminates the reflections and resonances.

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