HMI PCBA Design Guide: Touch and Display Integration for Industrial Human Machine Interface

1. Trace Shielding and Parasitic Capacitance Control for Capacitive Touchscreens
- Capacitance to Ground Plane (C_SG): If there is one layer of ground plane one 0.1mm from a sensor trace, then there will be .05-.02pF/centimeter. This is not a size that corresponds to the touch value.
- Mutual Coupling Between Channels: All of the PCAP (Projected Capacitive Touch) designs have some form of mutual coupling between the adjacent x/y electrodes, resulting in cross-talk artefacts that must be taken into account.
- Integrated Display-Touches: There are LCD COM switches for COM Electrode Switching Noise on LCD COM, which generates a very large, periodic and synchronous noise floor.
Hatched Ground Plane Design
Practical Routing Rules for HMI PCBA Layout
- Keep sensor traces short: The longer the traces, the higher is the parasitic capacitance added and the antenna surface area increased. Try to keep the traces of sensors as short as possible.
- Optimize the location of touch controller: The optimal placement of the touch controller IC should be near the FPC connector, keeping in view thermal issues.
- Use separate inner layer for touch routing: Use one half of a specific inner layer of PCB for touch routing with a driven shield plane on both sides of the layer. Do not route touch circuitry on static ground plane.
- Provide filtering to power supplies: Install a ferrite bead along with 100nF and 10uF capacitors in series in between AVDD and DVDD supply planes to touch controller. The purpose is to filter out any noise coupled from digital side of the touch controller to the analog sensing power supply.
- Perform touch measurements during LCD blanking: Perform touch measurements using the SYNC output of the touch controller during LCD blanking period only when COM lines are stable.
2. Layout Design for Backlight Driver Circuits Within LCD Modules
- Conducted noise – transferred via a common power line
- Radiated noise – transferred to touch sensor electrodes (antennas)
Critical Layout Rules for HMI PCBA Backlight Circuits
- Decrease power loop area: The fast current loop circuit consisting of the input capacitor, switching MOSFET, and catch diode must be placed on a single copper layer in the board with components kept as close as possible. The trace width must be at least 1.5mm with maximum current of 1A.
- Stacking of layers for a 4-layer board: Layer 2 must act as the Faraday shield between the noisy switching circuits in Layer 1 and the delicate touch routing in Layer 3. There should not be any route in Layer 1 close to the backlight driver.
| Layer | Task |
| L1 (Top) | Backlight driver components, short power connections |
| L2 | Solid, unbroken ground plane beneath driver |
| L3 | Power planes and touch sensor routing |
| L4(Bottom) | Display interface traces, secondary components |
- Establish a local ground moat: The placement of a ground island near the driver in Layer 1 and connection of the island through multiple vias to Layer 2 is needed. It must be connected to the main ground only at the component level to avoid noise current flowing through the ground plane.
- Filter the LED cable: A common mode choke (CMC) is needed on the board side of the LED connector with 10-22 nF C0G ceramic capacitors placed from LED+ to LED- conductors and from the connector to ground. The ground island of the filter needs to be connected to chassis ground instead of signal ground for highest common mode filtering.
- PWM dimming details: In order to avoid any visual flickering observed through the camera, high PWM frequencies greater than 1 kHz have to be used. In order to obtain low EMI signature, analog (DC) dimming using the feedback node or spread-spectrum PWM with frequency deviation of ±5 – 10% should be considered.
3. ESD Countermeasures Against Human Body Model Discharge per IEC 61000-4-2
Three-Layer ESD Protection Architecture
- Layer 1 – Mechanical/Panel Isolation: Attach the touch screen (either glass or bezel) to a grounded chassis via its edge. It will ensure the creation of a low-impedance path that will direct ESD current to the ground before getting to the PCB. Extra isolation for the FFC can be provided using cable wrappers or EMI-absorbing foam.
- Layer 2 – TVS Protection at Entry Points: Apply TVS diodes on all FPC connectors as well as touch sensor lines, display buses (such as MIPI DSI, LVDS) and power lines. TVS diodes must be installed not further than 2-3 mm from the connector on the same layer, preceding any series impedance.
- Capacitance: 0.3–1.5 pF per channel for high-speed interfaces (MIPI DSI up to 1.5 Gbps lanes). TVS diode arrays for multi-channel ESD protection, developed by manufacturers like Semtech, Littelfuse and ST, can be applied here.
- Clamping voltage (Vc): It must be lower than the absolute maximum rating of the protected IC, e.g. below 12 V for CMOS inputs at test current of 1 A.
- Response time: Silicon TVS has <1 ns response time. Metal oxide varistor (MOV) cannot be used as primary protection devices as MOVs usually have a delay of 25–50 ns.
- Bidirectional devices: Should be placed on the touch sensor lines as the ESD event occurs with a dual polarity (positive and negative).
- Layer 3 – Series Impedance and Local Decoupling: After the TVS device, series impedance in the range of 33 Ω to 100 Ω per sensitive signal line will need to be inserted to limit the peak current entering the ESD structures inside the IC. The remaining ESD impulse will be attenuated by the RC low pass filter which consists of the capacitance of the TVS diode and additional series impedance. 100 nF X7R ceramic capacitor (high frequency decoupling) and 10 µF ceramic/tantalum bulk capacitor (transient suppression) should be placed adjacent to the IC supply pins.
PCB Layout Rules for ESD Protection
- Design a short, straight, low impedance path for ESD to ground that doesn’t go near the ICs.
- Place the TVS diodes on the top layer between the connector and the IC. Make sure there is only one via (minimum diameter 0.3 mm) from the cathode end of each TVS diode to the ground plane.
- Use multiple points of connection to chassis ground (either 0 ohm jumper wires or mechanical standoffs) around the edge of the board to provide an ESD path.
- Do not have any slotted or discontinuous ground planes between the ESD entry points and the ICs—they add inductance that will make the design ineffective.
4. Voltage Regulation for Wide-Input Power Supplies in Industrial HMIs
Conversion Hierarchy
| Domain | Voltage | Key Requirements |
| Backlight LED string | 12-28V | Current accuracy ±5% |
| MIPI/LVDS display logic | 1.2V / 1.8V | Ripple < 10 mVpp |
| Touch controller AVDD | 2.8–3.3V | Ripple < 5 mVpp |
| Touch controller DVDD | 1.8V | Ripple < 20 mVpp |
| Processor core | 1.0–1.2V | Fast load transient |
- Stage 1: The first stage is a synchronous buck converter which converts input voltage from 24 V to intermediate voltage (12 V or 5 V).
- Select an IC with an absolute maximum input rating of at least 1.5× the expected peak transient (e.g., 60 V for 40 V peaks).
- Implement reverse polarity protection using a P-channel MOSFET ideal diode.
- Place a TVS clamp (e.g., P6KE33A) immediately adjacent to the input connector to limit voltage spikes from battery disconnection.
- Input capacitor bank: Combine 470–1000 µF of rated aluminum electrolytic capacitors with four 1210-package, 50 V, 4.7–10 µF MLCCs.
- Critical note: X7R MLCCs exhibit significant DC bias derating—a 10 µF/50 V ceramic capacitor may measure less than 2–3 µF at 24 V operating voltage. Verify loop compensation stability across the entire 19.2 V to 28.8 V input range, simulating at both voltage limits with worst-case component tolerances.
- Stage 2: Planning for post-regulation for noise critical domains at LDO. Power supply the touch controller AVDD and other noise sensitive supplies from an LDO that takes its power supply from the intermediate rail.
- Noise level < 30 µV rms (10 Hz – 100 kHz)
- PSRR > 60 dB at 100 kHz: To avoid that the switching noise of the backlight reaches the analog sensor supply.
- Provide LDO output with a 1 uF C0G ceramic (less than 0.5 mm separation from LDO output pin) and a 10 uF X5R ceramic. Because of the high humidity content of the wiring system, it is recommended to avoid using Tantalum capacitors as their failure mode (short circuit) can cause failures if shorted in the wiring system.
Input Protection Chain
- A MOSFET with reverse polarity is ideal for a diode controller, and has near zero voltage drop.
- TVS/MOV clamp: 33V clamping voltage, can capture the load-dump transient and EFT transient.
- For IEC 61000-4-4 (EFT) and 61000-4-5 (surge): Attenuation is provided in both cases.
- Two X capacitors (100 nF) + ferrite bead (100Ω at 100 MHz) are placed on both sides of the pi filter.
- The first is called bulk capacitance, which is the sum of the electrolytic and MLCC capacitance.
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Conclusion
FAQs about PLC PCBA
Use PWM frequencies above 1 kHz to eliminate visible flicker, particularly when cameras are used for inspection or monitoring (flicker below ~1 kHz is visible in video recordings). For minimal EMI, consider:
Analog (DC) dimming: Uses the feedback node directly—no PWM switching means zero PWM EMI, ideal for noise-sensitive touch applications
Spread-spectrum PWM: Varies the PWM frequency by ±5–10%, spreading energy across a wider bandwidth and reducing peak emissions
The trade-off is that analog dimming may have limited dimming range at low currents, while spread-spectrum introduces slight frequency variation that must be accommodated by the display driver.
Inductance is created in the ESD discharge circuit by a slotted or cut ground plane. At the very high frequencies that exist in an ESD discharge (GHz order of magnitude), even minimal inductance results in considerable impedance leading to:
- Increased voltage drops on the IC input
- Currents being diverted through improper routes
- Possibility of damage even when TVS components are used
The ESD discharge route needs to be kept short and direct with low inductance from the point of ESD entry to the chassis ground via TVS diodes, using multiple vias and with no cuts in the ground plane.
MIPI DSI displays require a specific power-on sequence to prevent damage and ensure proper initialization:
VCC_IO (I/O power) — first
VCC_CORE (core logic power) — second
VCC_LCD (display panel power) — third
VLED (backlight LED power) — fourth
Implement using either:
A PMIC with programmable sequencing delays
Cascaded enable pins (each stage’s enable controlled by the previous stage’s power-good output)
RC timers to add 100–500 ms inter-stage delays
Reverse sequencing during power-off (VLED off first, then VCC_LCD, etc.) is equally important to avoid latch-up or premature display failure.
For a human machine interface in PLC system, the HMI PCBA acts as the physical interface between the user and the programmable logic controller. Important integration points are as follows:
- Communication interface: The HMI PCBA should have reliable RS-232, RS-485, Ethernet or CAN transceivers to communicate with PLCs within the noisy environment of a factory
- I/O isolation: Opto-isolation/galvanic isolation should be provided on communication interfaces to avoid ground loops due to voltage difference between HMI and PLC
- Real-time performance: The HMI PCBA software should give priority to screen update and touch inputs and communicate with the PLC in the presence of network congestion
- Fail-safe operation: In cases where the HMI is being used as a control interface, it should be able to detect loss of connection to the PLC and put itself into a safe mode of operation
Industrial Human Machine Interface devices are increasingly functioning as edge computing nodes where data collected from PLC is visualized along with analysis carried out locally.
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